Classical co-processing & error correction

Fault tolerance turns quantum computing into a classical-silicon problem. An error-corrected machine streams syndrome measurements off the QPU continuously, and a decoder has to chew through them and return corrections inside the qubits' coherence budget — microseconds, for superconducting machines. At that latency you cannot decode in the cloud, or even down the hall: the classical compute must sit in the rack. That physical constraint is the chokepoint, and it holds no matter which qubit modality wins.

NVIDIA moved first to own the wire. NVQLink, launched October 2025, is an open-but-NVIDIA-shaped interconnect — sub-4-microsecond GPU-QPU round trip, 400 Gb/s — with 17 QPU builders, five controller vendors and nine US scientific labs signed on at launch (NVIDIA's "Nine Scientific Labs" — eight national laboratories plus MIT Lincoln Laboratory), and more than a dozen supercomputing centers across Asia and Europe joining three weeks later. At GTC in March 2026 it went generally available through the cudaq-realtime API in CUDA-Q 0.14, and Quantinuum's Helios has already run the first real-time decode of a qLDPC code through the stack with a 67-microsecond reaction time. This is the CUDA playbook rerun: standardize the interface before the market exists, then tax every workload that lands on it.

But watch the silicon that actually decodes today: it is mostly FPGA, and mostly AMD. IBM's Relay-BP decoder for its gross code fits on a single off-the-shelf AMD VU19P FPGA and runs ten times faster than real time — delivered a year ahead of IBM's own schedule — and the August 2025 IBM-AMD quantum-centric supercomputing partnership makes AMD the classical substrate for IBM's 2029 Starling machine. Beneath the megacaps sits a thin merchant layer: Riverlane, the leading pure-play decoder-silicon company, claims partnerships with over 60% of quantum hardware makers, and Quantum Machines owns the controller layer for more than half the industry and co-built DGX Quantum with NVIDIA.

The moat is latency physics plus co-design intimacy plus software gravity, and it is real. What breaks it is vertical integration: Google decodes its surface codes in-house, and IBM's choice of FPGAs over GPUs proves the GPU tier is optional for at least some codes. If controller-embedded ASIC decode proves sufficient — Riverlane's bet — NVIDIA's per-QPU attach shrinks to calibration, simulation and AI-assisted tuning. A genuine challenger would need both a low-latency open interface and a decoder ecosystem; only government programs could plausibly fund that from scratch.

Be honest about scale: this chokepoint's revenue is a rounding error for NVDA, AMD and IBM today — total quantum hardware spend is low-single-digit billions — and only the privates feel it in their P&L. You own this theme for optionality on the standard, not for earnings. The repricing event is DARPA's Quantum Benchmarking Initiative Stage C decisions, expected late 2026: the 11 Stage B teams must show a credible, risk-mitigated path to utility-scale fault tolerance by 2033 — which in practice means convincing real-time error correction — and selection effectively anoints the classical decode stacks the US government will fund through 2033. Watch NVIDIA's late-August print (the Aug 26 date is aggregator-sourced) and Riverlane's Deltaflow 3 "streaming logic" release in late 2026 as secondary marks.